Direct Digital Synthesizer Architecture Based on Amplitude Sequencing

The paper introduces an architecture for a direct digital synthesizer based on algorithmic direct amplitude generation. The circuit implementing the algorithm has a gate count proportional to digital precision length and in its simplest form includes one compare, one addition and several increments per iteration step. A phase compensation method is described to eliminate the nonuniformity in timing of the samples inherent to the algorithm. The paper also presents an analysis of the proposed architecture focusing on the amplitude samples timing accuracy versus generated signal frequency. A FPGA implementation of the architecture was simulated using a VHDL description to validate the solution as proposed . Key-Words: DDS amplitude centered architecture, Jordan's nonparametric curve generator, signal generation solutions in FPGA.